Research

Neural Networks | AI Hardware Accelerator | Computer Architecture | Low-Power VLSI Circuits

VLSI Circuits and Systems Research Group, AUST

Lab Head: Dr. Satyendra Nath Biswas

Professor, Department of EEE, AUST

Advisor, VLSI Lab, AUST

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The significance of power and energy usage in electronic gadgets has grown considerably. The proliferation of electronic gadgets has necessitated the development of low-power circuit designs. Insufficient power supply necessitates a reduction in the threshold voltage of transistors employed in electronic devices, hence giving rise to issues such as subthreshold leakage current. The gadget must undergo velocity saturation, and the threshold voltage exhibits increased sensitivity to temperature variations. Additionally, the reduction in voltage supply necessitates a decrease in the thickness of the gate oxide, resulting in gate leakage and power loss. Consequently, a multitude of power reduction solutions have emerged. Various techniques, such as multi-threshold devices (MTCMOS), variable multi-threshold devices (VTCMOS), and dynamic threshold devices (DTCMOS), have been developed. Furthermore, the utilization of device scaling has been employed. Among the several strategies considered, a particular approach was the utilization of a time-varying supply voltage as opposed to the traditional constant voltage supply. Taking this into consideration, the term "adiabatic" was coined to describe the use power devices.

The term "adiabatic" originates from the scientific principle of no exchange of energy with the surrounding environment. However, within the field of Very Large Scale Integration (VLSI), it refers to achieving the minimum amount of power dissipation in a circuit. In an optimal adiabatic circuit, the operation necessitates a low-frequency power source to facilitate the functioning of the circuit. In a complementary metal-oxide-semiconductor (CMOS) circuit, energy is transported only at voltage levels of either 0 or Vdd. The total power dissipated by the circuit can be expressed as CLVdd2.The output capacitance retains half of the product of the load capacitance and the square of the supply voltage.However, in the context of an adiabatic operation, the utilisation of a power clock (PC) is employed as an alternative to the provision of voltage Vdd. The energy dissipation during the switching process is reduced, resulting in a portion of the power from the load capacitance being transferred to the supply voltage. Theoretical maintenance of zero energy dissipation is possible in the Adiabatic process. Nevertheless, the reduction in transistor size has resulted in the emergence of some challenges, such as the occurrence of leakage current and energy dissipation caused by the flow of energy via a thin oxide layer. This is the reason why there is a growing body of research focused on enhancing adiabatic circuits.

1. Bhati and Preeti, "Adiabatic logic: an alternative approach to low power application circuits," in 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT). IEEE, 2016.

In this paper, an ECRL Circuit is proposed. Efficient Charge Recovery Logic (ECRL) uses pull-down NMOS devices on both sides to implement the truth table of the logic of any given circuit. It also uses two PMOS on the upper side of the circuit to hold the state as the full recovery of the power clock is not possible through these two PMOS, so it acts as quasi-adiabatic logic.

2. A. N. B. M. G. Debika Chaudhuri, "2N2N2P-An Efficient Adiabatic Logic for VLSI," International Journal of Innovative Research in Science,Engineering and Technology, pp. ISSN (Online) : 2319 - 8753,ISSN (Print) : 2347 - 6710, 2015.

This paper explains 2N2N2P NAND gate which belongs to a quasi-adiabatic logic family just like ECRL. Its main objective is to reduce the coupling effect. For the implementation of NAND/AND, two NMOS in series are on the left side of the pull-down, and two extra NMOS are in parallel to each other on the right side.

3. P. K. Chetan chugh, "A Novel Adiabatic Technique for Energy Efficient Logic Circuits Design," IEEE, pp. 5386-6483, 2018.

Here a Positive Feedback Adiabatic Logic (PFAL) NAND gate is depicted by using two NMOS parallel with the cross-coupled PMOS. It consumes the lowest energy than ECRL and 2N2N2P logic

Currently, we are working on Neural Network Processing Element Design also studying CNN, DNN, Artificial Intelligence, and Machine Learning to understand the mechanisms of Processing Element design and its properties. We are using DNN (Deep Neural Network) method to perform these analyses. 

Abstract: The term BIST, short for Built-In Self-Test, refers to a construction technique employed in hardware devices to carry out fault detection. Its purpose is to enhance the device's performance and establish a fault-free environment, hence preventing any potential damage during the device's operational lifespan. The need for distinct Built-In Self-Test (BIST) modules to perform memory testing and fault detection in various Integrated Circuits (ICs) introduces complexity in the design process, leading to increased power consumption and clock cycle duration. The authors offer a Built-In Self-Test (BIST) technique that effectively conducts memory testing and identifies problems by generating fault-detecting vectors. This research study additionally guarantees reduced power consumption during the testing phase. The proposed method offers a more efficient and innovative way for self-testing in comparison to numerous other existing Built-In Self-Test (BIST) solutions. This is achieved by reducing clock cycles and minimizing design complexity, hence mitigating the challenges encountered during hardware implementation.

Ultimately, the implementation of the new Built-In Self-Test (BIST) method for the development of a Random Pattern Generator, Memory, and Response Analyzer has been achieved. The Test Pattern Generator for the C-17 circuit encompasses a total of 32 test vectors that are utilized for circuit testing purposes. Subsequently, the designated test vectors are assessed, and the requisite test vector is reduced to a magnitude of 15 units. Subsequently, a random number generator (RPG) is employed to generate a set of 15 test vectors, which are then supplied as input to the C-17 benchmark circuit. The number of MOSFETs in the Memory design was correspondingly diminished by the reduced test vector. As a result, the circuit has exhibited enhanced efficiency and a reduction in power usage.

[You can find the full text of my B.Sc. thesis here]