Projects

As the technology is shrinking down day by day, power supply is also being scaled down thus different topologies of Static Random Access Memory (SRAM) cells are proposed so far, keeping the power consumption, leakage current, area of the cell and other parameters in mind. We have noticed that every cell topology had some drawbacks which were overcome by introducing another topology, so there are scopes to work on. In this project, the Layout we have implemented, can be improved, we will surely look into that and try to improve in our future works. Also here we have implemented the topologies with 90nm MOS technology by gpdk90 of Cadence. Thus in future there are many scopes to implement these cell topologies in other MOS technologies and also in FinFET and if possible, in Gate All Around(GAA) technology. So we are very much interested to work on SRAM cell architecture in future to get the best out of it. 

In this project, we designed 4 bit ALU with 8 arithmetic and logical functions those are Addition, Subtraction, 2 Bit Multiplication, AND, OR, NOR, NAND and XOR.

This is the main design of our whole circuit diagram. Instead of an induction motor, we used a light bulb for test purposes on the load side. One side of the 220-volt Ac supply is connected to the load, and the other side to the 6-ampere fuse. Power diodes of 1N4007 are used as a bridge rectifier connected in series with the load.

The source current flows through the bridge rectifier during the first half cycle. We have used power diodes only for the presence of an induction motor. Our IGBT_25N120 is open due to no response from the gate pulse. The current will go across the series connection of resistor R14(100-ohm-2-watt) and Capacitor C6(0.1-microfarad-400-volt).

This connection is called a snubber circuit. It is also known as a protection circuit. During zero gate pulse, the IGBT remains inactive. Without a snubber circuit, the whole voltage source can damage the IGBT, taking it to the breakdown region. So, to protect it, the whole current flows through the C6 capacitor, and it gets charged. Resistor R14 is used to slow the quick discharge of current to the IGBT after gate pulse, preventing considerable current flow through it.

After the source current passes through the bridge rectifier, it also flows through D4 and R11. Then, it follows two different paths. One direction of current flows across the two parallel poly star capacitors, i.e., C3 and C4, and the other flows through the series connection of the R10 and R9 resistor.

Across the poly star capacitors, i.e., C3 and C4, we will get a significant voltage drop of pulse setting dc. As our IGBT can take a maximum +20V gate voltage, we need to use a poly star capacitor for dropping the 224-volt to our required gate voltage. This voltage drop also depends on PWM that we applied earlier. Besides, the capacitors also play a role in filtering out the ac components.

On the other hand, the 224-volt DC gets a colossal voltage drop across the series connection of the R10 and R9 resistor. Both of them are 33k-ohm. We will get two different amounts of the voltage drop across the poly star capacitor and the R9 resistor.

As the PWM was applied and the base was active, the current will flow from collector to emitter. This current will flow across the Zener diode D5 and the capacitor C5. We used Zener diode 1N4742A, which will provide us constant 12-volt dc. 2.2 microfarad capacitor is used for smoothing the dc supply by filtering out the rest ac components.

The R13 resistor is a current limiting resistor that prevents the emitter from overflowing current. Now, the pure 12-volt DC will flow through R12 and D6 and move towards the input gate of IGBT_Q2, BJT_Q1, and the Emitter of BJT BC557.

Here D6(1N4148) is a fast-switching diode used for quicker response in the input gate of Mosfet and BJT. BC557 is a PNP transistor that activates in negative gate pulse. So, it won’t be activated with a positive 12-volt DC flow.

As the 12-volt DC activates the gate of IGBT, the current will flow from collector to emitter, making almost a short-circuit connection in practical analysis. In this stage, the left side of the circuit of IGBT will get zero voltage or remain inactive.

The charged current in the snubber circuit will discharge slowly from the collector to the Emitter of IGBT. As a result, the whole 224-volt dc source current will flow through the IGBT. Now, removing the gate pulse of IGBT does not affect the short-circuit connection, which is one of the properties of IGBT. But without controlling the switch of IGBT, we won’t get PWM Ac. This will happen to make the induction motor run forever. For this reason, BJT BC557 is used.

The 12-volt gate pulse of BJT discharges to the ground. In this state, the base of Q1 has 0 voltage. The 12-volt DC from the Q2 gate pulse will flow towards the Emitter of Q1 to the collector and discharge to the ground.

As a result, no current will flow from collector to emitter of IGBT because the gate pulse has no voltage drop. Our circuit will stop in this stage for 1 nanosecond. In this way, the whole cycle continues, and we get a proper PWM Ac curve which is our main motto of the project. 

An inverter is a fundamental circuit that transforms direct current (DC) into alternating current (AC) power at a desired voltage and frequency. Multiple tiers of inverters exist, such as Level-3, Level-5, and Level-7, among others. The level 7 inverter is utilized in this project. At advanced stages, there is a reduced presence of distortion. The method described herein has the potential to mitigate the presence of harmonics in the output waveform. This project presents the introduction of seven-level cascaded H-bridge inverters. The hardware system of the multilevel Cascaded H-Bridge inverter was evaluated by comparing its results across many factors, including the number of switches, the number of DC sources necessary for operation, and the total harmonic distortion (THD) levels. The comparative analysis shows that the seven-level inverter exhibits a lower total harmonic distortion (THD) level in contrast to the three- and seven-level inverters. Based on this comparison, it can be inferred that a rise in the number of levels is associated with a decrease in the degree of total harmonic distortion (THD). The utilization of H-bridges results in a reduction in harmonic content within the output of the inverter.

In this project, we have tried to design a simulation tool for the FDM system to simulate two different audio signals. For this purpose, different types of built-in functions are used, i.e., audio recorder, audio data, and audio write. Other types of filters are designed according to condition. We have assumed the IIR LPF to be a first-order filter. That’s why we have used that transfer function, which was described before. When maintaining bandgap, we have to do a trial & error method to find a suitable way for carrier frequency 2. The main challenge was selecting two cutoff frequencies for BPF for two different audio signals. We have overcome this problem by trial & error method. We have assumed the order as 50, both for FIR LPF & FIR BPF. We have used four different self-made functions to simplify our coding implementation. At the end of coding, we have coded so that one can listen to both audio signals before FDM & after FDM.

According to our project condition, we have to show – 1, 3, 5, 6 in a common anode type seven segment display. The display will be left blank for all logic combinations except for the logic conditions of 1, 3, 5, 6.