Publications

Abstract: Power and energy consumption of electronic devices have become very important. Due to the massive use of electronic devices, it has become important for designing low-power circuits. Low power supply means the threshold voltage of the transistors in electronic devices has to be decreased which in turn causes problems like subthreshold leakage current. The device needs to be velocity-saturated and also the threshold voltage becomes more reactive with the temperature change. Also due to the lower voltage supply, gate oxide needs to become thinner causing gate leakage and power dissipation. As a result, various power reduction techniques have come forward. Techniques like multi-threshold devices (MTCMOS), variable multi-threshold devices (VTCMOS), and dynamic threshold devices (DTCMOS) are used to design low power circuit. Also scaling of devices has been used. Out of these techniques, one technique was to use time-varying supply voltage instead of the conventional constant voltage supply. With this in mind, the term Adiabatic was introduced for using low-power devices. In this thesis paper, various adiabatic circuits have been explored. And a new type of adiabatic circuit has been proposed for low-power dissipation. Extensive simulation experiments have been carried out using Cadence and LTSpice software. The simulation results suggest the competency of the proposed model.

Abstract: VLSI circuit testing is complex and costs over 30% of the total IC design. The built-in self-testing technique is popular for its extensive fault coverage and efficiency. BIST refers to a hardware device testing construction used to perform fault detection and improve the device's performance to ensure a fault-free environment to avoid causing damage within the device's lifetime. As ICs are getting more complex day by day, different BIST modules are needed to test different circuits, which increase complication in design. As a result, power consumption and clock cycle increase. This research introduces a new Built-in Self-Test (BIST) technique for VLSI circuits. To deal with the shortcomings of conventional techniques, a BIST technique is proposed, which can test the circuit's functionality and detect faults successfully. The proposed model has been implemented using 22nm PTM model by employing LTSpice simulation software. The proposed model decreases power consumption upto 47.54% in without fault, 45.34% in open circuit fault and 45.63% in short circuit fault conditions compared to conventional technique and reduces the input vectors which in turn minimizes design intricacy and ensures an improved and novel approach for self-testing compared to many other existing BIST techniques. 

Abstract: Massive technological advancements are done on VLSI regarding propagation delay, performance analysis, and reducing channel length. As a result, electronic devices are becoming more portable nowadays. One of the significant concerns of VLSI is reducing the leakage current as the channel length is getting shorter day by day. As a result, the control of the gate of MOSFET over the channel length is weakening. So, a lot of leakage current passes over the entire MOSFET. To solve this problem, a new type of geometrical change is introduced in MOSFET. This innovation is known as Fully Depleted Silicon on Insulator (FD-SOI). Also, pass transistor logic is being used instead of conventional CMOS logic to reduce the chip device size. This paper focuses on reducing the no. of transistors and minimizing the power consumption simultaneously. In this manuscript a comprehensive analysis was done on Cadence Virtuoso 22nm FD-SOI technology where the proposed XNOR takes only 26% and proposed Full-Adder takes only 25% of the power consumption than conventional CMOS in different power supply. 

Abstract: In today's fast-paced technological era, electronic devices must be both speedy and energy-efficient to keep up with rapid advancements. Developing energy-efficient digital devices for real-time applications is critical in VLSI research. The adiabatic process of logic circuits is used to develop an adder with high performance and ultra-low power dissipation. Techniques like multi-threshold devices (MTCMOS), variable multi-threshold devices (VTCMOS), and dynamic threshold devices (DTCMOS) have been explored with the scaling of devices. The proposed circuit contains a new type of adiabatic circuit that works excellently for low-power dissipation. A comparison is made with the conventional CMOS adders, such as half and full adders and newly developed adiabatic logic circuits. All the experimental simulations have been carried out using LTSpice software for 16nm and 22nm LP PTM models by changing frequencies from 0MHz to 25MHz, taking rise and fall time as 1n & 2n seconds respectively. We have also varied the load capacitance from 0f to 10f. The outcomes obtained from the experiment indicate the effectiveness and capability of the newly proposed circuit, which is 40% less power consumption and 22% less energy consumption for both 16nm and 22nm, respectively, using 0f as load capacitance. 

Abstract: This paper discusses the low-power adiabatic models because the power and energy consumption increase of our used devices has become significant. In this thought, the solution of using the battery has become complex as a scale-down battery means a low power supply has to be given, and the threshold voltage of the transistors has to decrease. Techniques like multi-threshold devices (MTCMOS), variable multi-threshold devices (VTCMOS), and dynamic threshold devices (DTCMOS) come forward to mitigate the high-power consumption, which results in thinner gate-oxide, gate leakage, and power dissipation. The adiabatic technique is also one of the methods for reducing power in a device where a pulsating AC voltage is used instead of a constant voltage supply. This study proposes an adiabatic circuit for a NOR gate using a 32nm LP PTM Model. The comparative study, among the proposed circuit and PFAL, IPFAL, 2n2n2p, and ECRL used industry-standard software Cadence and LTSpice. Results show outstanding performance in power and energy dissipation as well as lower propagation delay in terms of the proposed inverter circuit, which is approximately 5.61% less than the adiabatic circuit 2N2N2P at 100MHz which has the lowest propagation delay other than the proposed inverter circuit. Power dissipation is reduced up to 77% in the proposed inverter circuit compared to the 2N2N2P adiabatic inverter circuit, which provides lower power among all the adiabatic circuits used in the experiment at 25MHz frequency. Similarly, the power dissipation for the proposed NOR circuit becomes 93% less than ECRL, which shows the lowest results after the proposed circuit at 25MHz frequency. 

Abstract: In this era of the 4th industrial revolution silicon industry plays the most important role. The power and energy consumption of VLSI devices has become an obstacle in the ways of developing advanced computers. Methods such as dynamic threshold devices (DTCMOS), variable multi-threshold devices (VTCMOS), and multi-threshold devices (MTCMOS) are proposed to counteract the reduced voltage supply, which leads to reduced power dissipation, thinner gate oxide, and gate leakage. Adiabatic was introduced out of these methods for using low-power devices by varying the voltage supply. In this study, a new type of ECRL circuit model is proposed. This circuit gives better performance in case of power and energy consumption compared to Conventional CMOS, traditional ECRL, and 2n2n2p. Simulations for comparison were done by industry-standard software like Cadence and LTSpice.